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Table 11-2:
UCF Location Constraints
Possible Potential Competing Devices on SPI_MISO (NF_D<0>) Data
Signal or
Jumper
Jumper J46
FPGA_INIT_B
SPI_SS_B
ALT_SS_B
Disabled Device
Platform Flash PROM.
SPI Flash PROM selected by
Jumper J1, as shown in
Table 12-2, page 93 .
SPI Flash PROM selected by
Disable Value
Set to “Disabled” or “Enable
during Configuration” as
shown in Table 4-2, page 40 .
FPGA_INIT_B has no effect.
If set to “Always Enabled,” then
FPGA_INIT_B must be 1
1
1
Jumper J1, as shown in
Table 12-2, page 93 .
UCF Location Constraints
Address
Figure 11-2 provides the UCF constraints for the Flash address pins, including the I/O pin
assignment and the I/O standard used.
NET "NF_A<24>" LOC = "A11" | IOSTANDARD = LVCMOS33 | DRIVE = 8 |
NET "NF_A<23>" LOC = "N11" | IOSTANDARD = LVCMOS33 | DRIVE = 8 |
NET "NF_A<22>" LOC = "V12" | IOSTANDARD = LVCMOS33 | DRIVE = 8 |
NET "NF_A<21>" LOC = "C21" | IOSTANDARD = LVCMOS33 | DRIVE = 8 |
NET "NF_A<20>" LOC = "C22" | IOSTANDARD = LVCMOS33 | DRIVE = 8 |
NET "NF_A<19>" LOC = "F21" | IOSTANDARD = LVCMOS33 | DRIVE = 8 |
NET "NF_A<18>" LOC = "F22" | IOSTANDARD = LVCMOS33 | DRIVE = 8 |
NET "NF_A<17>" LOC = "H20" | IOSTANDARD = LVCMOS33 | DRIVE = 8 |
NET "NF_A<16>" LOC = "H21" | IOSTANDARD = LVCMOS33 | DRIVE = 8 |
NET "NF_A<15>" LOC = "G22" | IOSTANDARD = LVCMOS33 | DRIVE = 8 |
NET "NF_A<14>" LOC = "H22" | IOSTANDARD = LVCMOS33 | DRIVE = 8 |
NET "NF_A<13>" LOC = "J20" | IOSTANDARD = LVCMOS33 | DRIVE = 8 |
NET "NF_A<12>" LOC = "J21" | IOSTANDARD = LVCMOS33 | DRIVE = 8 |
NET "NF_A<11>" LOC = "J22" | IOSTANDARD = LVCMOS33 | DRIVE = 8 |
NET "NF_A<10>" LOC = "K22" | IOSTANDARD = LVCMOS33 | DRIVE = 8 |
SLEW =
SLEW =
SLEW =
SLEW =
SLEW =
SLEW =
SLEW =
SLEW =
SLEW =
SLEW =
SLEW =
SLEW =
SLEW =
SLEW =
SLEW =
SLOW ;
SLOW ;
SLOW ;
SLOW ;
SLOW ;
SLOW ;
SLOW ;
SLOW ;
SLOW ;
SLOW ;
SLOW ;
SLOW ;
SLOW ;
SLOW ;
SLOW ;
NET "NF_A<9>"
NET "NF_A<8>"
NET "NF_A<7>"
NET "NF_A<6>"
NET "NF_A<5>"
NET "NF_A<4>"
NET "NF_A<3>"
NET "NF_A<2>"
NET "NF_A<1>"
NET "NF_A<0>"
LOC = "N17" | IOSTANDARD = LVCMOS33 | DRIVE = 8 |
LOC = "N18" | IOSTANDARD = LVCMOS33 | DRIVE = 8 |
LOC = "N19" | IOSTANDARD = LVCMOS33 | DRIVE = 8 |
LOC = "N20" | IOSTANDARD = LVCMOS33 | DRIVE = 8 |
LOC = "N21" | IOSTANDARD = LVCMOS33 | DRIVE = 8 |
LOC = "N22" | IOSTANDARD = LVCMOS33 | DRIVE = 8 |
LOC = "P18" | IOSTANDARD = LVCMOS33 | DRIVE = 8 |
LOC = "R19" | IOSTANDARD = LVCMOS33 | DRIVE = 8 |
LOC = "T18" | IOSTANDARD = LVCMOS33 | DRIVE = 8 |
LOC = "T17" | IOSTANDARD = LVCMOS33 | DRIVE = 8 |
SLEW =
SLEW =
SLEW =
SLEW =
SLEW =
SLEW =
SLEW =
SLEW =
SLEW =
SLEW =
SLOW ;
SLOW ;
SLOW ;
SLOW ;
SLOW ;
SLOW ;
SLOW ;
SLOW ;
SLOW ;
SLOW ;
# Upper four address lines, NF_A<25:22>, are unconnected using a
# They are available as user I/Os but do not connect to anything
CONFIG PROHIBIT = B22;
CONFIG PROHIBIT = B21;
CONFIG PROHIBIT = G18;
CONFIG PROHIBIT = G17;
32Mbit
on the
Flash
board
Figure 11-2:
UCF Location Constraints for Flash Address Signals
Spartan-3A/3AN FPGA Starter Kit Board User Guide www.xilinx.com
UG334 (v1.1) June 19, 2008
87
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